In conventional high-density semiconductor memory devices, a double metal process is generally used to improve the characteristics of the semiconductor memory elements. In a double metal process, before a second metal is formed, a reverse diode is formed at a gate of the transistors. In anticipation of damage incurred from a radio frequency (RF) etchback process, the gate is connected to a first metal through a via contact, to thereby dissipate charge into the substrate without building-up the charge on the gate. Accordingly, build-up of charge generated from the gate of the transistor during the etchback process is prevented.
Such methods may also be applied to a word line of a memory cell array which receives a gate signal through the second metal from a row decoder. The word line is connected to the first metal through a via contact, thereby causing shifting and degradation of the threshold voltage of the transistor due to the charge-up phenomenon in the RF etchback process. In order to prevent shifting and degradation of the threshold voltage, a reverse diode, also referred to as a "word line reverse diode", is formed at the word line.
Word line reverse diodes are described in publications entitled "Gate Oxide Charging and Its Elimination For Metal Antenna Capacitor and Transistor in VLSI CMOS Double Layer Metal Technology" by Shone et al., 1989 Symposium on VLSI Technology Digest of Technical Papers, May 22-25, 1989, Kyoto, Japan, pp. 73-74, and "The Effect of Charge Build-Up on Gate Oxide Breakdown During Dry Etching" by Tsunokuni et al., Extended Abstracts of the 19.sup.th Conference on Solid State Devices and Materials, Tokyo, 1987, pp. 195-198, the disclosures of which are hereby incorporated herein in their entirety by reference.
In semiconductor memory devices, the chip area is primarily occupied by the memory cell array. The area of the semiconductor occupied by the memory cell array may be increased by installing a ground voltage strapping line, a word line strapping line and the word line reverse diodes in the cell array of the semiconductor memory device. Also, unlike ground voltage strapping every eight cells, in the case of sixteen cell strapping, it is important to perform a well bias tapping at a portion of a well edge of a cell. Ground strapping lines are described in U.S. Pat. No. 5,293,559 to Kim et al., that is assigned to the assignee of the present application, the disclosure of which is hereby incorporated herein in its entirety by reference. Well bias tapping regions are described in U.S. Pat. No. 5,373,476 to Jeon, that is assigned to the assignee of the present application, the disclosure of which is hereby incorporated herein in its entirety by reference.
However, there have been problems because well bias tapping cannot be readily performed by installation of a diode, or in which the diode is omitted and in which a reverse diode is installed. These structures may increase the size of the semiconductor memory chip.